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r10ds0216ej0100 rev.1.00 page 1 of 12 2014.2.27 rmlv0414e series 4mb advanced lpsram (256-kword 16-bit) description the rmlv0414e series is a family of 4-mbit static rams organized 262,144-word 16-bit, fabricated by renesas?s high-performance advanced lpsram t echnologies. the rmlv0414e series has realized higher density, higher performance and low power consumption. the rmlv0414e series offers low power standby power dissipation; therefore, it is suitable for battery backup syst ems. it is offered in 44-pin tsop (ii). features ? single 3v supply: 2.7v to 3.6v ? access time: 45ns (max.) ? current consumption: standby: 0.4a (typ.) ? equal access and cycle times ? common data input and output three state output ? directly ttl compatible all inputs and outputs ? battery backup operation part name information part name access time temperature range package shipping container rmlv0414egsb-4s2#aa0 45 ns -40 ~ +85c 400-mil 44pin plastic tsop (ii) tray max. 135pcs/tray max. 1080pcs/inner box rmlv0414egsb-4s2#ha0 embossed tape 1000pcs/reel r10ds0216ej0100 rev.1.00 2014.2.27
rmlv0414e series r10ds0216ej0100 rev.1.00 page 2 of 12 2014.2.27 pin arrangement pin description pin name function v cc power supply v ss ground a0 to a17 address input i/o0 to i/o15 data input/output cs# chip select oe# output enable we# write enable lb# lower byte select ub# upper byte select nc no connection a4 a3 a2 a1 a0 cs# i/o0 i/o1 i/o2 i/o3 vcc vss i/o4 i/o5 i/o6 i/o7 we# a17 a16 a15 a14 a13 a 5 a6 a7 oe# ub# lb# i/o15 i/o14 i/o13 i/o12 vss vcc i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 a12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (top view) 44pin tsop (ii)
rmlv0414e series r10ds0216ej0100 rev.1.00 page 3 of 12 2014.2.27 block diagram operation table cs# we# oe# ub# lb# i/o0 to i/o7 i/o8 to i/o15 operation h x x x x high-z high-z standby x x x h h high-z high-z standby l h l l l dout dout read l h l h l dout high-z lower byte read l h l l h high-z dout upper byte read l l x l l din din write l l x h l din high-z lower byte write l l x l h high-z din upper byte write l h h x x high-z high-z output disable note 1. h: v ih l:v il x: v ih or v il memory matrix a1 a2 a3 a4 a6 a8 a13 a14 a15 a16 a17 2,048 x 2,048 row decode r ? ? ? ? ? input data control a 12 a11 a10 a9 a 7 a5 a0 ? ? ? ? ? ? i/o0 i/o15 cs# oe# v cc v ss control logic column i/o column decode r lb# ub# we#
rmlv0414e series r10ds0216ej0100 rev.1.00 page 4 of 12 2014.2.27 absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc -0.5 to +4.6 v terminal voltage on any pin relative to v ss v t -0.5 *2 to v cc +0.3 *3 v power dissipation p t 0.7 w operation temperature topr -40 to +85 c storage temperature range tstg -65 to +150 c storage temperature range under bias tbias -40 to +85 c note 2. -3.0v for pulse 30ns (full width at half maximum) 3. maximum voltage is +4.6v. dc operating conditions parameter symbol min. typ. max. unit note supply voltage v cc 2.7 3.0 3.6 v v ss 0 0 0 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il -0.3 0.6 v 4 ambient temperature range ta -40 +85 c note 4. -3.0v for pulse 30ns (full width at half maximum) dc characteristics parameter symbol min. typ. max. unit test conditions input leakage current | i li | 1 ? a vin = v ss to v cc output leakage current | i lo | 1 ? a cs# = v ih or oe# = v ih or we# = v il or lb# = ub# = v ih , v i/o = v ss to v cc operating current i cc 10 ma cs# = v il , others = v ih /v il , i i/o = 0ma average operating current i cc1 20 ma cycle = 55ns, duty =100%, i i/o = 0ma, cs# = v il , others = v ih /v il 25 ma cycle = 45ns, duty =100%, i i/o = 0ma, cs# = v il , others = v ih /v il i cc2 2.5 ma cycle =1 ? s, duty =100%, i i/o = 0ma cs# 0.2v, v ih v cc -0.2v, v il 0.2v standby current i sb 0.1 *5 0.3 ma cs# = v ih , others = v ss to v cc standby current i sb1 0.4 *5 2 ? a ~+25c vin = v ss to v cc , (1) cs# v cc -0.2v or (2) lb# = ub# v cc -0.2v, cs# 0.2v 3 ? a ~+40c 5 ? a ~+70c 7 ? a ~+85c output high voltage v oh 2.4 v i oh = -1ma v oh2 v cc -0.2 v i oh = -0.1ma output low voltage v ol 0.4 v i ol = 2ma v ol2 0.2 v i ol = 0.1ma note 5. typical parameter indicates the value for the cent er of distribution at 3.0v (ta=25oc), and not 100% tested. capacitance (vcc = 2.7v ~ 3.6v, f = 1mhz, ta = -40 ~ +85c) parameter symbol min. typ. max. unit test conditions note input capacitance c in 8 pf vin =0v 6 input / output capacitance c i/o 10 pf v i/o =0v 6 note 6. this parameter is sampled and not 100% tested.
rmlv0414e series r10ds0216ej0100 rev.1.00 page 5 of 12 2014.2.27 ac characteristics test conditions (vcc = 2.7v ~ 3.6v, ta = -40 ~ +85c) ? input pulse levels: v il = 0.4v, v ih = 2.4v ? input rise and fall time: 5ns ? input and output timing reference level: 1.4v ? output load: see figures (including scope and jig) read cycle parameter symbol min. max. unit note read cycle time t rc 45 ns address access time t aa 45 ns chip select access time t acs 45 ns output enable to output valid t oe 22 ns output hold from address change t oh 10 ns lb#, ub# access time t ba 45 ns chip select to output in low-z t clz 10 ns 7,8 lb#, ub# enable to low-z t blz 5 ns 7,8 output enable to output in low-z t olz 5 ns 7,8 chip deselect to output in high-z t chz 0 18 ns 7,8,9 lb#, ub# disable to high-z t bhz 0 18 ns 7,8,9 output disable to output in high-z t ohz 0 18 ns 7,8,9 note 7. this parameter is sampled and not 100% tested. 8. at any given temperat ure and voltage condition, t chz max is less than t clz min, t bhz max is less than t blz min, and t ohz max is less than t olz min, for any device. 9. t chz , t bhz and t ohz are defined as the time when the i/o pi ns enter a high-impedance state and are not referred to the i/o levels. i/o 1.4v r l = 500 ohm c l = 30 pf
rmlv0414e series r10ds0216ej0100 rev.1.00 page 6 of 12 2014.2.27 write cycle parameter symbol min. max. unit note write cycle time t wc 45 ns address valid to write end t aw 35 ns chip select to write end t cw 35 ns write pulse width t wp 35 ns 10 lb#,ub# valid to write end t bw 35 ns address setup time to write start t as 0 ns write recovery time from write end t wr 0 ns data to write time overlap t dw 25 ns data hold from write end t dh 0 ns output enable from write end t ow 5 ns 11 output disable to output in high-z t ohz 0 18 ns 11,12 write to output in high-z t whz 0 18 ns 11,12 note 10. t wp is the interval between write start and write end. a write starts when all of (cs#), (we#) and ( one or both of lb# and ub#) become active. a write is performed during the overlap of a lo w cs#, a low we# and a low lb# or a low ub#. a write ends when any of (cs#), (we#) or ( one or both of lb# and ub#) becomes inactive. 11. this parameter is sampled and not 100% tested. 12. t ohz and t whz are defined as the time when the i/o pins ente r a high-impedance state and are not referred to the i/o levels.
rmlv0414e series r10ds0216ej0100 rev.1.00 page 7 of 12 2014.2.27 timing waveforms read cycle note 13. t chz , t bhz and t ohz are defined as the time when the i/o pi ns enter a high-impedance state and are not referred to the i/o levels. 14. this parameter is sampled and not 100% tested. 15. at any given temperat ure and voltage condition, t chz max is less than t clz min, t bhz max is less than t blz min, and t ohz max is less than t olz min, for any device. t aa cs# a 0~17 t oh t clz t acs t oe t olz t chz oe# we# i/o 0~15 v ih t ohz we# = ?h? level t rc t blz t bhz lb#,ub# t ba high impedance valid data *14,15 *14,15 *14,15 *13,14,15 *13,14,15 *13,14,15 valid address
rmlv0414e series r10ds0216ej0100 rev.1.00 page 8 of 12 2014.2.27 write cycle (1) (we# clock, oe#=?h? while writing) note 16. t wp is the interval between write start and write end. a write starts when all of (cs#), (we#) and ( one or both of lb# and ub#) become active. a write is performed during the overlap of a lo w cs#, a low we# and a low lb# or a low ub#. a write ends when any of (cs#), (we#) or ( one or both of lb# and ub#) becomes inactive. 17. t ohz and t whz are defined as the time when the i/o pins ente r a high-impedance state and are not referred to the i/o levels. 18. this parameter is sampled and not 100% tested. 19. during this period, i/o pins are in the output st ate so input signals must not be applied to the i/o pins. cs# a 0~17 t cw t whz oe# we# i/o 0~15 t dh t wc lb#,ub# t bw valid address t wr t aw t as t wp t dw *16 *17,18 *17,18 t ohz valid data *19
rmlv0414e series r10ds0216ej0100 rev.1.00 page 9 of 12 2014.2.27 write cycle (2) (we# clock, oe# low fixed) note 20. t wp is the interval between write start and write end. a write starts when all of (cs#), (we#) and ( one or both of lb# and ub#) become active. a write is performed during the overlap of a lo w cs#, a low we# and a low lb# or a low ub#. a write ends when any of (cs#), (we#) or ( one or both of lb# and ub#) becomes inactive. 21. t whz is defined as the time when the i/o pins enter a high-impedance state and are not referred to the i/o levels. 22. this parameter is sampled and not 100% tested. 23. during this period, i/o pins are in the output st ate so input signals must not be applied to the i/o pins. cs# a 0~17 t cw t whz oe# we# i/o 0~15 t wc lb#,ub# t bw valid address t wr t aw t as t wp t ow *20 *21,22 valid data v il oe# = ?l? level *23 *23 t dh t dw
rmlv0414e series r10ds0216ej0100 rev.1.00 page 10 of 12 2014.2.27 write cycle (3) (cs# clock) note 24. t wp is the interval between write start and write end. a write starts when all of (cs#), (we#) and ( one or both of lb# and ub#) become active. a write is performed during the overlap of a lo w cs#, a low we# and a low lb# or a low ub#. a write ends when any of (cs#), (we#) or ( one or both of lb# and ub#) becomes inactive. cs# a 0~17 t cw oe# we# i/o 0~15 t dh t wc lb#,ub# t bw valid address t wr t aw t as t wp t dw v ih oe# = ?h? level *24 valid data
rmlv0414e series r10ds0216ej0100 rev.1.00 page 11 of 12 2014.2.27 write cycle (4) (lb#,ub# clock) note 25. t wp is the interval between write start and write end. a write starts when all of (cs#), (we#) and ( one or both of lb# and ub#) become active. a write is performed during the overlap of a lo w cs#, a low we# and a low lb# or a low ub#. a write ends when any of (cs#), (we#) or ( one or both of lb# and ub#) becomes inactive. cs# a 0~17 t cw oe# we# i/o 0~15 t dh t wc lb#,ub# t bw valid address t wr t aw t as t wp t dw v ih oe# = ?h? level *25 valid data
rmlv0414e series r10ds0216ej0100 rev.1.00 page 12 of 12 2014.2.27 low v cc data retention characteristics parameter symbol min. typ. max. unit test conditions *27 v cc for data retention v dr 1.5 v vin 0v, (1) cs# v cc -0.2v or (2) lb# = ub# v cc -0.2v, cs# 0.2v data retention current i ccdr 0.4 *26 2 ? a ~+25c v cc =3.0v, vin 0v, (1) cs# v cc -0.2v or (2) lb# = ub# v cc -0.2v, cs# 0.2v 3 ? a ~+40c 5 ? a ~+70c 7 ? a ~+85c chip deselect time to data retention t cdr 0 ns see retention waveform. operation recovery time t r 5 ms note 26. typical parameter indicates the value for the cent er of distribution at 3.0v (ta=25oc), and not 100% tested. 27. cs# controls address buffer, we # buffer, oe# buffer, lb# buffer, ub # buffer and i/o buffer. if cs# controls data retention mode, vin le vels (address, we#, oe#, lb#,ub#, i/o) can be in the high -impedance state. low vcc data retention timing waveforms (cs# controlled) low vcc data retention timing waveforms (lb#,ub# controlled) cs# v cc cs# controlled t cdr t r 2.7v 2.7v 2.2v 2.2v v dr cs# v cc -0.2v lb#,ub# v cc lb#,ub# controlled t cdr t r 2.7v 2.7v 2.2v 2.2v v dr lb# , ub# v cc -0.2v
all trademarks and registered trademarks are t he property of their respective owners. revision history rmlv0414 e series data sheet rev. date description page summary 1.00 2014.2.27 first edition issued
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